1. Field of the Invention
The present invention relates to an insulated-gate field-effect transistor having a suppressed short channel effect, particularly to a double-gate field-effect transistor, and to an integrated circuit employing the transistor and a method of manufacturing the transistor.
2. Description of the Prior Art
In order to achieve insulated-gate field-effect transistors with shorter channel lengths, it is necessary to suppress the short channel effect (the threshold voltage roll-off that occurs when the channel length is shortened). The double-gate field-effect transistor disclosed by Japanese Patent No. 2,021,931 has a device structure for achieving that. FIG. 1 is a cross-sectional view of a conventional double-gate field-effect transistor.
With reference to FIG. 1, the transistor includes a substrate 501, a lower gate insulation film 502, a source region 503, a drain region 504, a channel region 505, an upper gate insulation film 506, an insulation film 507, an upper gate electrode 508, a lower gate electrode 509, a source electrode 530, and a drain electrode 540. This structure is a highly effective method of suppressing the short channel effect. This is because the upper gate electrode 508 and the lower gate electrode 509 shield the channel region 505. By thereby suppressing the effect that the drain field has on the potential distribution at the interface region between the source and the channel, it is possible to stabilize just the channel potential, even if the channel is shortened, thereby suppressing the threshold voltage roll-off caused by the short channel effect.
However, to enable this feature of the structure to function effectively in a high-performance integrated circuit device, there must be no positional misalignment between the channel region and the two gate electrodes. Misalignment increases parasitic capacitance and resistance that, together with the fluctuations thereof, can lead to a marked degradation in device performance.
With the structure of the conventional double-gate field-effect transistor in which the vertically arranged gate electrodes, separated by the channel region, together with the source and drain regions, are not provided on the same principal surface, self-alignment cannot be employed, making it difficult to form the two gate electrodes in alignment with the channel, source and drain regions. It has therefore been necessary to utilize the available positioning accuracy with respect to the disposition of the lower gate electrode and channel region, and this has given rise to the problem of performance degradation arising from such factors as increased parasitic capacitance and fluctuations thereof. Another drawback is that when the fabrication is used as an integrated circuit device, because the upper and lower gate electrodes are not positioned on the same principal surface, the wiring becomes complex. To resolve such problems, the present invention proposes a double-gate field-effect transistor having the configuration shown in the plan view of FIG. 2 and the cross-sectional view of FIG. 3.
With further respect to the double-gate field-effect transistor of this configuration, normally chemical mechanical polishing (CMP) is used for surface planarization. CMP and other planarizing processes can easily cause contamination and damage, and are followed by washing that itself involves many process steps. It is therefore desirable to reduce the number of planarizing steps as much as possible. Thus, another object of the present invention is to reduce the number of steps used to planarize surfaces using CMP and the like.